Flow Hardware Implementation
real-time motion estimation is very critical to
many computer vision tasks. However, because of
its computational power and processing speed
requirements, it is rarely used for real-time
applications, especially for micro unmanned
vehicles. In our previous work, a FPGA system
was built to process optical flow vectors of 64
frames of 640×480 image per second. Compared to
software-based algorithms, this system achieved
much higher frame rate but marginal accuracy. In
this paper, a more accurate optical flow
algorithm is proposed. Temporal smoothing is
incorporated in the hardware structure which
significantly improves the algorithm accuracy.
To accommodate temporal smoothing, the hardware
structure is composed of two parts: the
derivative (DER) module produces intermediate
results and the optical flow computation (OFC)
module calculates the final optical flow
vectors. Software running on a built-in
processor on the FPGA chip is used in the design
to direct the data flow and manage hardware
components. This new design has been implemented
on a compact, low power, high performance
hardware platform for micro UV
applications. It is able to process 15
frames of 640×480 image per second and with much
improved accuracy. Higher frame rate can be
achieved with further optimization and
additional memory space.
David and Deborah Huber Scholarship
B.E. Nelson, Z.Y. Wei, D.J. Lee, and J. Chase,
“A Comparison Study On
Implementing Optical Flow and Digital
Communications on FPGAs and GPUs,” ACM
Transactions on Reconfigurable Technology and
Systems, vol. 3/2, Article 6, 22 pages, May
Wei, D.J. Lee, B.E. Nelson, and J.K.
Accurate Optical Flow-based Motion Sensor,”
IEEE International Conference on Pattern
Recognition (ICPR), Tampa, FL, USA, p. 1-4,
doi: 10.1109/ICPR.2008.4761126, December 8-11,
Wei, D.J. Lee, B.E. Nelson, J.K.
Archibald, and B.B. Edwards, "ʺFPGA-Based
Embedded Motion Estimation Sensor,"
International Journal of Reconfigurable
Computing, vol. 2008, Article ID 636145, 8
pages, July 2008.
Chase, B.E. Nelson, J.M. Bodily,
Z.Y. Wei, and D.J. Lee, “FPGA and GPU
Architectures For Real-Time Optical Flow
Calculations,”, IEEE Symposium
on Field-Programmable Custom Computing
Machines (FCCM), p. 173-182, Palo Alto, CA,
USA, April 14-15, 2008.
image to view.)