In most circumstances, determining an acceptable tradeoff between speed and accuracy when selecting a stereo vision algorithm for implementation, is dependent upon the target application. This work attempts to provide perspective on the efficiency of existing real-time stereo vision algorithms in terms of this tradeoff. This work also provides an example of modifying an existing highly accurate stereo vision algorithm to increase its runtime performance while trying to limit the loss in accuracy. Such an example demonstrates the challenge of making efficient tradeoffs in accuracy for runtime performance. It is shown that the modifications resulted in an 8X speedup over the original algorithm, with accuracy results comparable to existing real-time
algorithms. 

      An efficient stereo vision hardware design implemented on an FPGA would be able to minimize payload and power consumption on micro-UVs, while providing them with 3D information and still leaving computational resources available for other processing tasks. This work presents a hardware design of the efficient Profile Shape Matching stereo vision algorithm. Hardware resource usage was presented for the targeted Heliocopter platform that uses the Xilinx Virtex 4 FX60 FPGA. Less than a fifth of the resources on this FGPA were used to produce dense disparity maps for image sizes up to 450 x 375, with the ability to scale up easily by increasing BRAM usage. A comparison is given of accuracy, speed performance, and resource usage of a Census transform based stereo vision FPGA implementation by Jin et al. Results show that the Profile Shape Matching algorithm is an efficient real-time stereo vision algorithm for hardware implementations for resource limited systems such as micro unmanned vehicles.

 Graduate Students:

  Beau Tippetts and Kirt Lillywhite